Why do ASIC DFT guys get much higher packages than design verification?

Every ASIC designer starts with verification tasks. Verify functionality and learn about testbenches and automation (regression, self-checking). View a lot of RTL files and after a while also RTL design will be one of your skills. RTL and verification (behavioural) are all about a language (HDL) and EDA tools (simulators, compilers, …). But synthesis will link the HDL code to gates. Here digital design insight is needed. If then will be translated in a (priority) mux. A case statement will be an all-equal mux. Comparators, addition, substraction, multipliers, dividers, counters, … . DFT is a gain a step-up. Testmodes are there for functional (silicon) tests, to debug and for test (check if the chip is good after packaging or on the die itself). You need to know how a netlist (RTL translated by synthesis tool) looks like to stitch scan chains together, control all resets and clocks, … . Hence the level of experience and knowledge is much higher than for verification.


Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.
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