Why are initial blocks synthesizable in FPGA and not in ASIC?

We are describing hardware, this means logic gates )which have no memory and flipflops. Flops are clocked memory elements. They have a clock, the rythm of change and a reset which brings them in a default state, binary 0 or 1. A hardware description language is describing hardware (duh) and the idea has always been to be independent of target tech and/or EDA vendor. An inital state as such is not real in hardware, it is a behavioursal thing. In non-synthesizable code, it make sense to assign an inital value to start with a known value, behavioural coding has no hardware equivalent. RTL code, the synthesizable code is targeted at hardware. Even though an FPGA powers up and uses the power on reset (POR) to bring the FPGA in a known state, that depends on the EDA vendor and the target tech, in this case FPGA. I know the big FPGA vendors do support this, but it goes against the agnostic HDL philosophy. And if you ask an FPGA designer, the initial statement is used for having an inital value in simulation, not having red undefined or X signals on the waveform. FPGA architecture is such that for max speed, the flops benefit from not having a reset. And if a reset is needed for a safe start state, synchronous reset would be preferred. A long story to show the spcific difference between ASIC design and FPGA design. An ASIC is just logic gates, not predefined macros that are powered on in acontrolled way like an FPGA. All ASIC flops need an asynchronous reset for DFT purposes (scan chains and test patterns). And an ASIC powers up but it is the ASIC designer that needs to bring the ASIC in a safe state. Initial is not linked to a signal or port, it has no meaning whatsoever in an ASIC. An ASIC has a clock and reset module which takes care of the safe state. The POR, power on reset, let’s say an RC connected to an input of the ASIC, is used in the clock and reset module to distribute this reset to all flops when the power is switched on. Also, in case of emergency, the whole chip can be reset, example a reset button that is an input to the ASIC. Even though a clock might fail, oscillator defect, the ASIC reset is asynchronous and brings all internal states but also the ASIC output pins into a safe state even without a clock present (asynchronous!). Outputs can reset to high-impedant to avoid that they are driven from the ASIC and from another source on the PCB. The point is that in ASIC design, the code is written as if reset, then safe state. If not reset, then if clock edge then do the functionality you want. For me initial statements are allowed in behavioural but I would never use them myself in RTL. Nowadays, every ASIC is prototyped in FPGA and sometimes FPGA designs will be used later on for an ASIC. Therefor, I always try to be independent of tools and tech and not use initial in RTL, since for ASIC it does not make sense.


Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.
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