What is the difference between floor planning in FPGA, Standard Cell Based Design (ASIC) and Gate Array?

I will oversimplify a bit. A gate array is mainly just a bunch of logic. An ASIC is a result of a netlist (logic gates, flops and wires connecting them, produced by the frontend team), the layout team will take the netlist and based on the pinout, the location of the chip pins, will make a rough floorplan or placement of the hierarchy of the netlist. For multi million gates ASIC designs, the tools can place any logic element on N locations, the next one on N-1 locations and so on. A bit oversimplified, but the tool has an impossible number of combinations to try out. Of course there are algorithms that bring more intelligence to the placement but in essence, a human is still the best initial floorplanner. If the tool has a good starting point where it is guided to place certain submodules of the design close to the IO pins it needs together with a shape and surrounding shapes of the surrounding modules, the tools have a good starting point and do amuch faster and better job of doing a first placement. In principle, an ASIC has the most freedom for placement. An FPGA is actually an ASIC, which has configurability, it is a fixed layout with logic elements (different vendors have different terminology) but basically there are blocks with gates and flipflops that are the smallest element you can use in the FPGA floorplanner. There could also be memory blocks (and dedicated DSP blocks) but mainly you have a kind of array of lego that you can interconnect (done by the tools) the way you need it. FPGA tools are run by the frontend designer, so no separation between frontend and backend here. And FPGA tools have leave less control to the user. The free version of the tools takes the IO pin positions and the logic netlist and tries to map it according to your constraints (timing and area). You can set the effort from small to medium to hard (latter is slowest). You can tweak a bit but you have almost no control on the floorplan, where the tool will place certain logic or submodules. In the paid version, there are ways of defining areas with a size and a coordinate to give the tool a precise area to use and lock it. So the FPGA designer is at the same time the place and route person too and if he has the paid version of the tools he can do a kind of floorplan if it is required (but I have seen enough FPGA designs that did not need this at all). For ASIC, there is a dedicated layout team with the required expertise to floorplan the ASIC which is required to get to a placement which matches the requirements fast. The experience of the layout person will define the time needed to get to a final placement that passes all checks, more experienced layout people will make a far better initial floorplan and get to a passing placement faster.


Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.
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