Every ASIC designer starts his career as verification engineer. They learn the syntax of one or more HDL’s, hardware description languages like VHDL and verilog. The syntax of these languages has behavioural and RTL implementations. RTL means that the code can be translated by a synthesis tool into hardware, gates and flops. Behavioural code is not necessarily synthesizable and for testbenches for example, it doesn’t need to be synthesizable. Hence a verification engineer does not need to worry about the synthesizability of his code. He writes testbenches and runs simulations. A designer needs more experince with HDL’s, he understands the subset of the HDL that is synthesizable and knows the relationship between his code and the hardware. He can already foresee timing issues by coding accordingly, for example pipeline arithmetic algotihms. A desgner needs a text editor, scripting experience, simulation experience and digital logic knowledge (including synthesis). A verification engineer needs a text editor, some scritping experience and use a simulator.