Verification has come a long way. Today UVM, has replaced most EDA vendor specific methodologies and a de facto standard. Systemverilog and UVM are skills that are almost required for ASIC digital verification jobs. While most do not go further than this, there are some things worth mentioning. The concept of universal and methodology is great. But the down side of everything general is that it could be less efficient for certain verification tasks, projects or whatever. The learning curve is quite steep for junior engineers. And I have seen many huge models with millions of config parameters in classes of classes of classes. And in the end, the testcases diverts from the original leveled approach to just hacking the testcase until it works. Just a superficial and shallow observation, because the matter is more complex, but as such, every system has its advantages and disadvantages. Be aware of both!