What is linting in ASIC design? Why is it used?

Linting is an EDA tool or program (whatever you like) that analyzes the RTL code that was written. It is specifically the RTL, so the synthesizable code that is analyzed. Every language has a syntax but there is always a synthesizable subset that excludes behavioural code that cannot be synthesized by the current EDA tools. The linting is usually ran when doing the compile and elaboration of the simulations. A lint tool analyzes based on a configuration or set of rules. The rules are broad so that you can catch anything from small problems to big issues that you want to solve now and not later in the flow. Every company has rules it wants to be PASS before the code is accepted. And they also have rules they don’t care about or are nice to have but not required. So, these rules pertain to syntax, to synthesis and DFT, all the steps following later in the flow towards a netlist. You can use the lint check to catch things early. But, as I said before, the use of the tool and the definition of the rules and the gravity of a FAIL is user defined. Per company or per team in a company, these rules are defined.


Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.
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