The verilog syntax can be mastered by googling verilog tutorials. That’s free. The paid courses could be a course from Doulos or a similar training company. But there is nobody going to teach you the best practices, the methodology and how verilog fits in the whole design cycle of FPGA or ASIC. Knowing the syntax and some concepts like RTL vs behavioural does not make you a verilog designer or verification engineer. That you need to learn doing that job. And even then, it depends on the company and team that you work with how good your skill will get. 99% of ASIC and FPGA design companies use the quantity approach. When the deadline gets closer and the project gets behind, they will put more resources on the project and make the resources work more hours. There is not one second spent on the efficiency improvement of a project. Even though there are some simple things that can make a huge difference.
Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.