Is there any future for Asynchronous VLSI design?

Asynchronous means not related to a clock. Synchronous design, everything going from IO or flop output through asynchronous logic to the next flipflop or IO, makes big designs simpler to manage. For STA, you can put timing constraints between flop to flop based on the clock. The asynchronous part between the flops is covered by this. For IO to flop or flop to IO, there will be requirements based on IO pad delay and PCB routing capacitance for example. Still, for certain calculations or optimizations, for example in CPU’s, it could be better for performance to not have that synchronous restriction. Some specific timing critical asynchronous paths are hand made. Not by a HDL and synthesis (tool chooses the logic cells). There are other specific uses for asynchronous design for power, area or speed (these three factors are alsways the ones that need a compromise, faster means more area and or more power consumption). Every clock toggle on a flop clock input has power implications (and EMC) but today synchronous design is gating of clocks to reduce this downside of synchronous design. Conclusion: yes, there is a future, but it will be and stay niche.


Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.
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