Asynchronous VLSI design means the logic has no relationship to a clock rhythm. While in a synchronous design, everything goes from register output through asynchronous logic to the next register. So it is constrained to a clock period. It makes big designs simpler to manage. For STA, you can put timing constraints between registers based on the clock period. The asynchronous part between the flops has one clock period of time to ripple from input to output. From and to the input-output (IO), there are special constraints.
Still, for certain calculations or optimizations, for example in CPU’s, it could be better for performance to not have that synchronous restriction. Some specific timing critical asynchronous paths need hand design. Not by a HDL and synthesis (tool chooses the logic cells). There are other specific uses for asynchronous design for power, area or speed (these three factors are alsways the ones that need a compromise, faster means more area and or more power consumption). Every clock toggle on a flop clock input has power implications (and EMC) but today synchronous design is gating of clocks to reduce this downside of synchronous design. Conclusion: yes, there is a future, but it will be and stay niche.
Quora space : HW accelerators eating AI