No, since verilog is not an embedded programming language, it is a language with a syntax that describes hardware (hence the term HDL). While it looks like programming, it definitely is not. Embedded software is either low level assembler or c/C++ compiled for the instruction set of the embedded processor. So, these programs are software, but verilog is not. The hardware it describes is verified with testbenches, then synthesized which means translated into a netlist (gates and flops). For FPGA (reconfigurable) place and route follows. For ASIC, static timing analysis, DFT insertion and simulation and pre and post layout gatelevel simulations are done. Sometimes also formal verification, RTL vs post and pre layout netlist.