First of all, the FPGA vendor itself, like Altera/Intel and Xilinx offer these solutions. Hardcopy is a solution where the FPGA is loaded with the programming you designed and then the whole programmbility is removed to reduce the size and consumption (a bit simplified I know). It is basically the frozen FPGA design. This is the fastest but not most optimal solution. The other solution (and I think they also offer this) is to port the design to an ASIC technology. Basically the design is changed so that resets, memories and otherr tech specific things are replaced. Then the whole ASIC process needs to take place. Verification, synthesis, STA, DFT, netlist, … . An ASIC design company can do that.