Programming an FPGA does not mean programming in c++. Hardware is described in a hardware description language, and there have been many efforts to use c and c++ for a HDL. And it exists. But programmers use a lot of constructs and algorithms that are simply not synthesizable in logic. A HDL is specifically designed for hardware types and a subset of the syntax that synthesis tools support and can be translated into HW. But even if the synthesis tool can synthesize for example a multiplier, that doesn’t mean that that implementation meets the area or speed requirements of the design. Writing FPGA dsigns in C++ does not solve the problem of software programmers’ lack of in depth knowledge of the hardware it generates and the ways to meet area or timing requirements. So, in short, yes, it is possible. No, it doesn’t make SW people succesful FPGA designer unless they train themselves or are trained to link syntax to hw based on boolean algebra.
Hardware and software advisor for tech startups. ASIC, FPGA, RPi, Arduino, AI, robots, drones, blockchain, Machine learning, vision processing, IoT and 3D printers are my fields of expertise.