ASIC RTL design is for people that an ASIC project costs tens of millions of dollars and needs to be first time right. It requires deep understanding of methodology to reduce risk for bugs to the lowest level possible. RTL is 25% design and 75% verification generally speaking. For FPGA, the same rules apply but unfortunately the nature of the FPGA is making people a bit lazy. The FPGA is reconfigurable with any digital design that fits. Hence, it is custom to do less verification by simulation and more on the FPGA itself.
An ASIC designer doing FPGA needs to get familiar with some specific FPGA things like the FPGA memories, DSP blocks and the basic blocks (LUT, LE, CLB, …) of the FPGA. Also, he needs to understand the different reset and clock requirements. So there is some effort from ASIC to FPGA, but nothing problematic. From FPGA to ASIC, there is a step-up which is far more difficult. ASIC memories, PLL’s, pads, clocks and clock trees, resets, memBist, scan chains, … . That is not mastered in a day or two. And as said before, the margin for error is tiny, everything needs to be simulated in detail and it needs to be thorough. Yes, it can be done, but it requires quite some effort, the other direction is way simpler.
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