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At present, which language is mostly used by VLSI companies, Verilog or SystemVerilog for RTL or ASIC design?

The trend is towards systemverilog for everything since both testbenches and RTL code can be written in the same HDL language, no need for mixed language licenses anymore. Of course legacy code and other factors require the companies to buy mixed language licenses but in theory systemverilog has everything to simulate and design.

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